1. Field of the Invention
This invention relates generally to wafer-level packages and multiple vertically stacked semiconductor structures for integrated circuits and, more particularly, to a wafer-level packages and multiple vertically stacked semiconductor structures for integrated circuits that includes a support structure positioned relative to a probe pad so as to prevent wafer damage during circuit testing.
2. Discussion of the Related Art
It is known in the art to provide wafer-level packages for integrated circuits, such as monolithic millimeter-wave integrated circuits (MMIC), formed on substrate wafers. In one wafer-level packaging design, a cover wafer is mounted to the substrate wafer using a bonding ring so as to provide a hermetically sealed cavity in which the integrated circuit is provided. Typically, many integrated circuits are formed on the substrate wafer and covered by a single cover wafer, where each integrated circuit is surrounded by a separate bonding ring. The cover wafer and the substrate are then diced between the bonding rings to separate the packages for each separate integrated circuit. The dicing process typically requires the use of a saw that cuts the cover wafer between the packages where a portion of the cover wafer is removed. The substrate wafer is then cut between the packages.
For certain wafer-level packaging designs, vias are provided through the substrate wafer that make electrical contact with signal lines and ground lines electrically coupled to the integrated circuit within the cavity. Probe pads formed on top of the substrate wafer are electrically coupled to certain ones of the vias opposite to the cavities, and a probe is electrically coupled to the probe pads so as to test the integrated circuit for performance purposes. The probe is typically part of a probe assembly, where the probe assembly can include multiple signal and/or ground probes or a combination of the two. The probe assembly is connected to a machine that automatically moves the probe assembly across the substrate wafer to provide electrical contact to a certain group of the probe pads for testing purposes.
The probe assembly applies a force to the substrate wafer to make a suitable electrical contact thereto. Because the substrate wafer is relatively thin, the force typically causes the substrate to flex, and may cause the substrate wafer to crack, thus affecting the hermetical seal of the cavity and the integrity of the wafer-level package.